1/9 june 2001 n high speed: t pd = 5.7ns (typ.) at v cc =5v n low power dissipation: i cc =4 m a (max.) at t a =25 c n high noise immunity: v nih =v nil = 28% v cc (min.) n power down protection on inputs n symmetrical output impedance: |i oh |=i ol = 8 ma (min) n balanced propagation delays: t plh @ t phl n operating voltage range: v cc (opr) = 2v to 5.5v n pin and function compatible with 74 series 138 n improved latch-up immunity description the 74vhc138 is an advanced high-speed cmos 3 to 8 line decoder (inverting) fabricated with sub-micron silicon gate and double-layer metal wiring c 2 mos technology. if the device is enabled, 3 binary select (a, b, and c) determine which one of the outputs will go low. if enable input g1 is held low or either g2a or g2b is held high, the decoding function is inhibited and all the 8 outputs go to high. tree enable inputs are provided to ease cascade connection and application of address decoders for memory systems. power down protection is provided on all inputs and 0 to 7v can be accepted on inputs with no regard to the supply voltage. this device can be used to interface 5v to 3v. all inputs and outputs are equipped with protection circuits against static discharge, giving them 2kv esd immunity and transient excess voltage. 74vhc138 3 to 8 line decoder (inverting) pin connection and iec logic symbols order codes package tube t & r sop 74vhc138m 74vhc138mtr tssop 74VHC138TTR tssop sop
74vhc138 2/9 input equivalent circuit pin description truth table x : don't care pin no symbol name and function 1, 2, 3 a, b, c address inputs 4, 5 g2a, g2b enable inputs 6 g1 enable input 15, 14, 13, 12, 11, 10, 9, 7 y0 to y7 outputs 8 gnd ground (0v) 16 v cc positive supply voltage inputs outputs enable select g2b g2a g1 c b a y0 y1 y2 y3 y4 y5 y6 y7 xxl xxxhhhhhhhh xhxxxxhhhhhhhh hxxxxxhhhhhhhh l lhl l l lhhhhhhh l lhl lhhlhhhhhh l lhlhlhhlhhhhh l lh lhhhhh lhhhh l lhhl l hhhhl hhh l lhhlhhhhhh lhh l lhhhl hhhhhhl h l lhhhhhhhhhhh l
74vhc138 3/9 logic diagram this logic diagram has not be used to estimate propagation delays absolute maximum ratings absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied recommended operating conditions 1) v in from 30% to 70% of v cc symbol parameter value unit v cc supply voltage -0.5 to +7.0 v v i dc input voltage -0.5 to +7.0 v v o dc output voltage -0.5 to v cc + 0.5 v i ik dc input diode current -20 ma i ok dc output diode current 20 ma i o dc output current 25 ma i cc or i gnd dc v cc or ground current 75 ma t stg storage temperature -65 to +150 c t l lead temperature (10 sec) 300 c symbol parameter value unit v cc supply voltage 2 to 5.5 v v i input voltage 0 to 5.5 v v o output voltage 0 to v cc v t op operating temperature -55 to 125 c dt/dv input rise and fall time (note 1) (v cc = 3.3 0.3v) (v cc = 5.0 0.5v) 0 to 100 0to20 ns/v
74vhc138 4/9 dc specifications ac electrical characteristics (input t r =t f = 3ns) (*) voltage range is 3.3v 0.3v (**) voltage range is 5.0v 0.5v symbol parameter test condition value unit v cc (v) t a =25 c -40 to 85 c -55 to 125 c min. typ. max. min. max. min. max. v ih high level input voltage 2.0 1.5 1.5 1.5 v 3.0 to 5.5 0.7v cc 0.7v cc 0.7v cc v il low level input voltage 2.0 0.5 0.5 0.5 v 3.0 to 5.5 0.3v cc 0.3v cc 0.3v cc v oh high level output voltage 2.0 i o =-50 m a 1.9 2.0 1.9 1.9 v 3.0 i o =-50 m a 2.9 3.0 2.9 2.9 4.5 i o =-50 m a 4.4 4.5 4.4 4.4 3.0 i o =-4 ma 2.58 2.48 2.4 4.5 i o =-8 ma 3.94 3.8 3.7 v ol low level output voltage 2.0 i o =50 m a 0.0 0.1 0.1 0.1 v 3.0 i o =50 m a 0.0 0.1 0.1 0.1 4.5 i o =50 m a 0.0 0.1 0.1 0.1 3.0 i o =4 ma 0.36 0.44 0.55 4.5 i o =8 ma 0.36 0.44 0.55 i i input leakage current 0to 5.5 v i = 5.5v or gnd 0.1 1 1 m a i cc quiescent supply current 5.5 v i =v cc or gnd 44040 m a symbol parameter test condition value unit v cc (v) c l (pf) t a =25 c -40 to 85 c -55 to 125 c min. typ. max. min. max. min. max. t plh t phl propagation delay time a, b, c, to y 3.3 (*) 15 8.2 11.4 1.0 13.0 1.0 13.0 ns 3.3 (*) 50 10.0 15.8 1.0 18.0 1.0 18.0 5.0 (**) 15 5.7 8.1 1.0 9.5 1.0 9.5 5.0 (**) 50 7.2 10.1 1.0 11.5 1.0 11.5 t plh t phl propagation delay time gtoy 3.3 (*) 15 8.1 12.8 1.0 15.0 1.0 15.0 ns 3.3 (*) 50 10.6 16.3 1.0 18.5 1.0 18.5 5.0 (**) 15 5.6 8.1 1.0 9.5 1.0 9.5 5.0 (**) 50 7.1 10.1 1.0 11.5 1.0 11.5 t plh t phl propagation delay time g2a, g2b to y 3.3 (*) 15 8.2 11.4 1.0 13.5 1.0 13.5 ns 3.3 (*) 50 10.7 14.9 1.0 17.0 1.0 17.0 5.0 (**) 15 5.8 8.1 1.0 9.5 1.0 9.5 5.0 (**) 50 7.3 10.1 1.0 11.5 1.0 11.5
74vhc138 5/9 capacitive characteristics 1) c pd is defined as the value of the ic's internal equivalent capacitance which is calculated from the operating current consumption without load. (refer to test circuit). average operating current can be obtained by the following equation. i cc(opr) =c pd xv cc xf in +i cc test circuit c l =15/50pf or equivalent (includes jig and probe capacitance) r t =z out of pulse generator (typically 50 w ) waveform 1: propagation delays for inverting outputs (f=1mhz; 50% duty cycle) symbol parameter test condition value unit t a =25 c -40 to 85 c -55 to 125 c min. typ. max. min. max. min. max. c in input capacitance 6101010pf c pd power dissipation capacitance (note 1) 34 pf
74vhc138 6/9 waveform 2:propagation delaysfor non-inverting outputs (f=1mhz;50% dutycycle)
74vhc138 7/9 dim. mm. inch min. typ max. min. typ. max. a 1.75 0.068 a1 0.1 0.2 0.003 0.007 a2 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 c 0.5 0.019 c1 45 (typ.) d 9.8 10 0.385 0.393 e 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 8.89 0.350 f 3.8 4.0 0.149 0.157 g 4.6 5.3 0.181 0.208 l 0.5 1.27 0.019 0.050 m 0.62 0.024 s8 (max.) so-16 mechanical data po13h
74vhc138 8/9 dim. mm. inch min. typ max. min. typ. max. a 1.2 0.047 a1 0.05 0.15 0.002 0.004 0.006 a2 0.8 1 1.05 0.031 0.039 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0089 d 4.9 5 5.1 0.193 0.197 0.201 e 6.2 6.4 6.6 0.244 0.252 0.260 e1 4.3 4.4 4.48 0.169 0.173 0.176 e 0.65 bsc 0.0256 bsc k0 8 0 8 l 0.45 0.60 0.75 0.018 0.024 0.030 tssop16 mechanical data c e b a2 a e1 d 1 pin 1 identification a1 l k e 0080338d
74vhc138 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringe ment of patents or other righ ts of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this pub lication are subject to change without notice. thi s pub lication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authori zed for use as critical components in life suppo rt devices or systems without express written approval of stmicroelectronics. ? the st logo is a registered trademark of stmicroelectronics ? 2001 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco singapore - spain - sweden - swit zerland - united kingdom ? http://w ww.st.com 9/9
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